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Renesas Electronics /R7FA6M3AH /PDC /PCDR

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Interpret as PCDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PCDR

Description

PDC Receive Data Register

Fields

PCDR

The PDC includes a 32-bit-wide, 22-stage FIFO for the storage of captured data. The PCDR register is a 4-byte space to which the FIFO is mapped, and four bytes of data are read from the PCDR register at a time.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data